1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an MOS structure (a structure having a channel region selectively formed in the main surface of a semiconductor substrate, a set of source/drain regions selectively formed in the main surface of the semiconductor substrate with the channel region therebetween, and a gate electrode facing the channel region through a gate insulating film), and particularly to an improvement for compatibly realizing reduction in leakage current and increase in gate insulating film reliability.
2. Description of the Background Art
FIGS. 55 and 56 are manufacturing process diagrams showing a conventional method for manufacturing a semiconductor device having the MOS structure, i.e., an insulated-gate semiconductor device. Particularly, this semiconductor device is constructed as an MOS transistor. In this specification, according to the common usage in this field of art, xe2x80x9cMOS transistorxe2x80x9d and xe2x80x9cMOS structurexe2x80x9d generally also include those having gate electrodes formed of conductors other than metal.
FIG. 55 is a front section of an intermediate structure obtained before formation of the gate electrode and FIG. 56 is a front section of an intermediate structure obtained after formation of the gate electrode. In the process shown in FIG. 55, first, an STI (Shallow Trench Isolation) 102 is formed in the main surface of the semiconductor substrate 101. The STI 102 is formed by selectively forming a trench having a depth of about 0.2 to 0.3 xcexcm in the main surface of the semiconductor substrate 101 and then burying an insulating film in the trench. The STI 102 is formed to separate a set of adjacent elements. In this specification, STI as a structure and STI as an element isolation method are both represented as xe2x80x9cSTI.xe2x80x9d
Subsequently, a well implantation and a channel-cut implantation are performed to form a well layer and a channel-cut layer in the semiconductor substrate 101. FIG. 55 does not show the well layer and the channel-cut layer.
Next, a gate insulating film 103 is formed on the main surface of the semiconductor substrate 101. The gate insulating film 103 is formed as a silicon oxide film by performing a thermal oxidation in an H2O atmosphere, O2 atmosphere, N2O atmosphere, NO atmosphere, or NO/O2 atmosphere, for example. The gate insulating film 103 may be formed by depositing a high-dielectric-constant film such as Ta2O5. The gate insulating film 103 usually has a thickness of about 1.5 to 8 nm, though it depends on the rated value of the power-supply voltage.
Deposited next on the gate insulating film 103 are a film of polysilicon 104 doped with phosphorus at a concentration of 5xc3x971020/cm3 and having a thickness of 0.1 xcexcm, a WSix (tungsten silicon compound; x=2, 3) film 105 having a thickness of 0.1 xcexcm, and an insulating film 106 having a thickness of 0.05 xcexcm, in this order. These films are deposited by using CVD (Chemical Vapor Deposition). The gate electrode is formed later from the two-layer structure of the polysilicon film 104 and the WSix film 105. In other cases, the gate electrode may be formed by using a metal material, such as W and Co, in place of the polysilicon/WSix two-layer structure.
Next, resist (photoresist) is applied on the insulating film 106 and then the resist is patterned by a transfer process to form a resist 107. The insulating film 106 is deposited on the WSix film 105 for the purpose of preventing halation, specifically, to prevent the phenomenon in which the resist 107 is finished in smaller size than the transferred mask due to reflecting light from the layer underlying the resist in the transfer process. The insulating film 106 can serve to prevent halation because the insulating film 106 has a smaller reflectance than the WSix film 105.
Next, the process shown in FIG. 56 is performed. In the process of FIG. 56, first, an anisotropic etching is performed by using the resist 107 as a mask to selectively remove the insulating film 106, the WSix film 105, and the polysilicon film 104. As a result, the gate electrode 110 is formed as a two-layer structure having the polysilicon film 104 and the WSix film 105. Reactive ion etching (RIE) is used as the anisotropic etching for forming the gate electrode 110.
After that, impurity ions are selectively implanted into the main surface of the semiconductor substrate 101 by using the gate electrode 110 and the insulating film 106 thereon as masks. As a result, in the main surface of the semiconductor substrate 101, source/drain layers (the generic name of the source layer and the drain layer) 111 are formed in the source/drain regions (the generic name of the source region and the drain region) 109 opposing through the channel region 108 right under the gate electrode 110.
In the conventional MOS transistor, the gate electrode 110 and the source/drain layers 111 are formed as described above. For example, when the MOS transistor is of n-channel type, the conductivity type of the channel region 108 is p type and the conductivity type of the source/drain layers 111 is n type.
As shown in FIG. 56, in the anisotropic etching process for forming the gate electrode 110, the polysilicon film 104, the WSix film 105, and the insulating film 106 are selectively removed in the areas located above the source/drain regions 109 and the STI 102. In this process, the resist 107 used as a mask is etched away, too. In the anisotropic etching, over etching is implemented to prevent the resist 107 from partially remaining unremoved.
When the over etch starts, the insulating film 106, the WSix film 105, and the polysilicon film 104 located above the source/drain regions 109 have been already removed by etching, with only the insulating films 103b remaining. While the resist 107 is mainly etched in the over etching, part of the insulating film 106 and part of the gate insulating films 103b are etched, too. Accordingly, the insulating films 103b on the source/drain regions 109 become thinner than the gate insulating film 103a on the channel region 108.
In reactive ion etching, CF4 becomes radicals in the form of CFx (x=1, 2, 3) in a plasma, and then they are accelerated by electric field in the ion sheath and transported to the surface of the WSix 105 and polysilicon film 104, which form the gate electrode 110. Then the radicals cut the bonds of Wxe2x80x94Si, Sixe2x80x94Si, etc. and remove silicon components and tungsten components in the form of SiF2, WF2, etc.
At the same time, the radicals accelerated in the electric field and energized enter the oxide film, silicon, etc. for about 10 nm depth at the maximum. Then, as the insulating films 103b become thinner, the following phenomena become more serious: the radicals (CFx) enter the main surface of the semiconductor substrate 101 to form levels (i.e., donor or acceptor levels), radiation damage (damage caused by radiation) occurs in the main surface of the semiconductor substrate 101 and the gate insulating film, and W atoms (or ions) emitted from the WSix 105 by sputtering enter the main surface of the semiconductor substrate 101 to form levels. The damaged layers 112 shown in FIG. 56 represent the radiation-damaged and level-formed layers in the main surface of the semiconductor substrate 101.
While most of the radiation damage is annealed out (eliminated by annealing) in thermal treatment process performed later in a nitrogen atmosphere, C, W, and the like remain near the main surface of the semiconductor substrate 101. When these levels are covered by a depletion layer, then SRH (Shockley-Read-Hall) current and TAT (Trap Assisted Tunnel) current increase, both of which cause leakage current in gate-off state. According to simulation, it is known that the electric field strength is as high as 5xc3x97105 V/cm or more in the gate end regions 113 (FIG. 56) when the gate is off. Particularly, since the TAT current exponentially increases with the electric field strength, the leakage current becomes considerably large due to the formation of levels. The increase in leakage current increases the power consumed when the semiconductor device is in the stand-by state. This problem is especially serious when the semiconductor device is used in portable electronic equipment which operates with battery.
Aside from this problem, Japanese Patent Laying-Open No.2-47838 discloses a semiconductor device manufacturing method in which, for the purpose of enhancing the breakdown voltage between the gate electrode and drain electrode, the insulating film on the source/drain regions is formed thicker than that on the channel region before reactive ion etching process for forming the gate electrode. FIGS. 57 and 58 are manufacturing process diagrams showing the manufacturing method disclosed in the reference.
In the process shown in FIG. 57, first, the STI 102 is selectively formed in the main surface of the semiconductor substrate 101 and then a well implant and a channel-cut implant are performed. This forms a well layer and a channel-cut layer in the semiconductor substrate 101. FIG. 57 does not show the well layer and the channel-cut layer.
Next, the gate insulating film 103 is formed as an oxide film on the main surface of the semiconductor substrate 101 and then a nitride film (silicon nitride film) 114 is deposited thereon. Subsequently, resist is applied on the nitride film 114 and the resist is patterned through a transfer process. Then the nitride film 114 is selectively removed by etching using the patterned resist as a mask. As a result, as shown in FIG. 57, the nitride film 114 remains unremoved only above the channel region 108.
Next, the process shown in FIG. 58 is performed. In the process of FIG. 58, first, a thermal treatment is performed in an oxidation atmosphere to form the gate insulating films 120 and 121 on the main surface of the semiconductor substrate 101. During this process, in the channel region 108, the nitride film 114 prevents the oxidizing agent from moving to the main surface of the semiconductor substrate 101, so that the oxidation rate in the channel region 108 is lower than that in the source/drain regions 109. Accordingly, the gate insulating film 120 on the channel region 108 becomes thinner than the gate insulating films 121 on the source/drain regions 109. Then bird""s beaks 115 are formed at the connections between the gate insulating film 120 and the gate insulating films 121.
Since the gate insulating films 121 on the source/drain regions 109 are formed thicker in the manufacturing method shown in FIGS. 57 and 58, this method provides not only the effect of enhancing the breakdown voltage between the gate electrode and drain electrode but also the effect of alleviating the trouble from which the manufacturing method shown in FIGS. 55 and 56 has been suffering, that is, it also provides the effect of suppressing the increase in leakage current caused as the gate insulating film 103 is over etched. However, since large stresses occur at and near the bird""s beaks 115 in the manufacturing method of FIGS. 57 and 58, the interface level density is high at and near the bird""s beaks 115, leading to another problem of shorter lifetime of the gate insulating film 120.
According to the first aspect of the present invention, in a method of manufacturing a semiconductor device having a channel region selectively formed in a main surface of a semiconductor substrate, a set of source/drain regions selectively formed in the main surface of the semiconductor substrate with the channel region interposed therebetween, and a gate electrode facing the channel region through a gate insulating film, the method comprises: (a) a step of preparing the semiconductor substrate; (b) a channel position selecting step of selectively introducing nitrogen into the main surface of the semiconductor substrate in an area which corresponds to the channel region; (c) an oxidation step of, after the channel position selecting step, oxidizing the main surface of the semiconductor substrate to form an insulating film on the main surface so that the insulating film is formed thicker on the set of source/drain regions than on the channel region; (d) a step of depositing an electrode material on the insulating film; and (e) a gate formation step of selectively removing the electrode material by using a selective etching to form the gate electrode.
According to the second aspect of the present invention, in a method of manufacturing a semiconductor device having a channel region selectively formed in a main surface of a semiconductor substrate, a set of source/drain regions selectively formed in the main surface of the semiconductor substrate with the channel region interposed therebetween, and a gate electrode facing the channel region through a gate insulating film, the method comprises: (a) a step of preparing the semiconductor substrate; (b) a step of oxidizing the main surface of the semiconductor substrate to form an insulating film on the main surface; (c) a channel position selecting step of depositing a polycrystalline semiconductor film and a semiconductor nitride film in this order on the insulating film in an area located above the channel region; (d) an oxidation step of, after the channel position selecting step, oxidizing the main surface of the semiconductor substrate so that the insulating film becomes thicker in the set of source/drain regions than in the channel region; (e) a step of removing the polycrystalline semiconductor film and the nitride film; (f) a step of depositing an electrode material on the insulating film; and (g) a gate formation step of selectively removing the electrode material by using a selective etching to form the gate electrode.
According to the third aspect of the present invention, in a method of manufacturing a semiconductor device having a channel region selectively formed in a main surface of a semiconductor substrate, a set of source/drain regions selectively formed in the main surface of the semiconductor substrate with the channel region interposed therebetween, and a gate electrode facing the channel region through a gate insulating film, the method comprises: (a) a step of preparing the semiconductor substrate; (b) a channel position selecting step of introducing an impurity into the main surface of the semiconductor substrate in areas which correspond to the set of source/drain regions at such a concentration that enhanced reaction occurs in oxidation reaction; (c) an oxidation step of, after the channel position selecting step, oxidizing the main surface of the semiconductor substrate to form an insulating film on the main surface so that the insulating film is formed thicker in the set of source/drain regions than in the channel region; (d) a step of depositing an electrode material on the insulating film; and (e) a gate formation step of selectively removing the electrode material by using a selective etching to form the gate electrode.
Preferably, by the step (b), the source/drain regions are formed.
According to the fourth aspect of the present invention, in a method of manufacturing a semiconductor device having a channel region selectively formed in a main surface of a semiconductor substrate, a set of source/drain regions selectively formed in the main surface of the semiconductor substrate with the channel region interposed therebetween, and a gate electrode facing the channel region through a gate insulating film, the method comprises: (a) a step of preparing the semiconductor substrate; (b) a step of oxidizing the main surface of the semiconductor substrate to form an insulating film on the main surface; (c) a channel position selecting step of applying a selective etching to selectively remove the insulating film on the channel region; (d) an oxidation step of, after the step (c), oxidizing the main surface of the semiconductor substrate to form on the channel region an insulating film thinner than the insulating film on the set of source/drain regions; (e) a step of depositing an electrode material over the insulating films on the channel region and the source/drain regions; and (f) selectively removing the electrode material by using a selective etching to form the gate electrode.
Preferably, the step (c) comprises: (c-1) depositing a semiconductor oxide film on the insulating film; (c-2) depositing a semiconductor nitride film on the semiconductor oxide film; and (c-3) applying selective etching to selectively remove the semiconductor nitride film, the semiconductor oxide film, and the insulating film over the channel region.
According to the fifth aspect of the present invention, in any one of the first to fourth aspects, the semiconductor device manufacturing methods further comprise a step (A) of heating at a temperature of 950xc2x0 C. or higher after the oxidation step.
According to the sixth aspect of the present invention, in any one of the first to fourth aspects, the semiconductor device manufacturing methods further comprise a step (B) of forming a mark in an area other than the channel region and the source/drain regions in the main surface of the semiconductor substrate, wherein positioning in the process in the channel position selecting step and positioning of the mark in the step (B) are achieved by transferring a common mask pattern, and in the gate formation step, the position in which the electrode material is selectively removed is determined through transfer of another mask pattern, and the another mask pattern is positioned on the basis of the position of the mark.
According to the seventh aspect of the present invention, in the sixth aspect, a trench is formed as the mark in the step (B).
Preferably, in the step of depositing the electrode material, the electrode material is also deposited on an inner surface of the trench, and the method further comprises a step of: (C) after the step of depositing and before the gate formation step, removing the electrode material from the inner surface of said trench.
Preferably, in the oxidation step, the insulating film is also formed on an inner surface of the trench, and in the step (C) the insulating film is also removed from the inner surface of the trench.
According to the eighth aspect of the present invention, in a method of manufacturing a semiconductor device having a channel region selectively formed in a main surface of a semiconductor substrate, a set of source/drain regions selectively formed in the main surface of the semiconductor substrate with the channel region interposed therebetween, and a gate electrode facing the channel region through a gate insulating film, the method comprises: (a) a step of preparing the semiconductor substrate; (b) a step of oxidizing the main surface of the semiconductor substrate to form an insulating film on the main surface; and (c) a channel position selecting step of applying a selective etching to selectively remove the insulating film on the channel region; wherein the step (c) comprises: (c-1) depositing a film on the insulating film; and (c-2) applying selective etching to selectively remove the film deposited in the step (c-1) and the insulating film over the channel region, and said method further comprises: (d) an oxidation step of, after the channel position selecting step, oxidizing the main surface of the semiconductor substrate to form on the channel region an insulating film thinner than the insulating film on the set of source/drain regions; (e) a step of depositing an electrode material over the insulating films on the channel region and the source/drain regions; (f) a gate formation step of polishing the electrode material so as not to leave the same on the film deposited in the step (c-1) but to selectively leave over the channel region to form the gate electrode; and (g) removing the film deposited in the step (c-1).
Preferably, the method further comprises a step (A) of heating at a temperature of 950xc2x0 C. or higher after the step (e).
According to the manufacturing method of the first aspect, the insulating film is formed thicker in the source/drain regions than in the channel region because the oxidation reaction is suppressed in the nitrogen-introduced region. This suppresses introduction of levels (i.e., donor or acceptor levels) into the source/drain regions in the gate formation step, thus reducing the leakage current of the completed semiconductor device. Furthermore, since the insulating film uneven in thickness is formed by utilizing a difference in oxidation reaction rate between the nitrogen-introduced region and other region, stresses caused in the insulating film by the oxidation can be reduced. This suppresses an increase in interface level density around the insulating film corresponding to the gate insulating film, thus improving the reliability of the gate insulating film.
According to the manufacturing method of the second aspect, the insulating film is formed thicker in the source/drain regions than in the channel region because the oxidation reaction is suppressed in the region covered with the semiconductor nitride film. This suppresses introduction of levels into the source/drain regions in the gate formation step, thus reducing the leakage current of the completed semiconductor device. Furthermore, since the semiconductor nitride film covers the channel region through the polysilicon film, stresses caused in the insulating film by the oxidation can be suppressed. This suppresses an increase in interface level density around the insulating film corresponding to the gate insulating film, thus improving the reliability of the gate insulating film.
According to the manufacturing method of the third aspect, the insulating film is formed thicker in the source/drain regions than in the channel region because the oxidation reaction is promoted in the impurity-introduced region. This suppresses introduction of levels in the source/drain regions in the gate formation step, thus reducing the leakage current of the completed semiconductor device. Furthermore, since the insulating film uneven in thickness is formed by utilizing a difference in oxidation reaction rate between the impurity-introduced region and other region, stresses caused in the insulating film by the oxidation can be suppressed. This suppresses an increase in interface level density around the insulating film corresponding to the gate insulating film, thus improving the reliability of the gate insulating film.
According to the manufacturing method of the fourth aspect, the insulating film is formed thicker in the source/drain regions than in the channel region. This suppresses introduction of levels into the source/drain regions in the gate formation step, thus reducing the leakage current of the completed semiconductor device. Furthermore, stresses caused at the insulating film by the oxidation can be suppressed, since the insulating film uneven in thickness is formed by once forming an insulating film, selectively removing the insulating film, and then selectively forming a thinner insulating film. This suppresses an increase in interface level density around the insulating film corresponding to the gate insulating film, thus improving the reliability of the gate insulating film.
According to the manufacturing method of the fifth aspect, the thermal treatment at a temperature of 950xc2x0 C. or higher further suppresses the occurrence of stresses in the insulating film by the effect of viscous fluidity of the insulating film.
According to the manufacturing method of the sixth aspect, the gate electrode can accurately be formed above the channel region in the gate formation step because the mask pattern is positioned on the basis of the mark. Furthermore, since the positioning in both of the formation of the mark and the channel position selecting step is achieved through a transfer of a common mask pattern, the mask pattern used in the gate formation step can be positioned with sufficiently reduced error.
According to the manufacturing method of the seventh aspect, since a trench is formed as the mark, a side surface of a step can be used as the mark. Accordingly the mark can be detected easily and the alignment can be achieved precisely.
According to the manufacturing method of the eighth aspect, the gate electrode is formed through xe2x80x9cdamascene methodxe2x80x9d with a reduced leakage current and an improved reliability of the gate insulating film.
The present invention has been made to solve the above-described problems in the conventional manufacturing methods, and an object of the present invention is to provide a semiconductor device manufacturing method which can compatibly realize reduction in leakage current and improvement of gate insulating film reliability.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.